发明名称 KEY INPUT CIRCUIT
摘要 PURPOSE:To realize a key input circuit with low power consumption suitable for a key telephone system by using a current source charging a capacitor intermittently. CONSTITUTION:A current source I1 charges intermittently a capacitor C11 in the timing impressed to a terminal T7 and a current source I2 discharges the capacitor C11 in the mid-timing of signal impressed to the terminal T7. When a switch SW is turned off, latch circuits L1, L2 fetching a data by using strobe signals STB1, STB2 output respectively '1', '0' because the said capacitor keeps the charge/discharge state respectively. On the other hand, when the switch SW is turned on, each capacitor repeats charging/discharging simultaneously. In setting a strobe signal STB2 while each capacitor is in the charging state, the output of the latch circuit L2 goes to '1' and in setting the strobe signal STB1, the output of the latch circuit L1 goes to '0'. Thus, the presence of the switching of the switch SW is detected by a circuit with low power consumption.
申请公布号 JPS62264720(A) 申请公布日期 1987.11.17
申请号 JP19860108815 申请日期 1986.05.12
申请人 NEC CORP 发明人 INUZUKA TERUO
分类号 H03K17/00;G06F3/02;H03K17/687 主分类号 H03K17/00
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