发明名称 CLOCK SIGNAL SWITCHING CIRCUIT
摘要 <p>PURPOSE: To prevent hazard from being generated at the time of clock signal switching by applying hysteresis corresponding to two clock signals to a select signal at the time point of switching clock signals at a selector control part. CONSTITUTION: Concerning select signals SL1 and SL2, a selector control part 2 applies the select signal SL1 for turning off the clock signal to a selector 1 as a select signal S1 synchronized with a clock signal CK1. Besides, the select signal SL2 for turning on the clock signal is applied to the selector 1 as a select signal S2, to which the hysteresis corresponding to two clock signals is applied, synchronized with a clock signal CK2. Thus, even when the phases of the clock signals CK1 and CK2 are shifted about at 360 deg., the generation of hazard caused by the switching of the clock signals CK1 and CK2 can be surely prevented. Even when switching other clock signals CK3-CKn, the generation of hazard can be prevented by the similar operation as well.</p>
申请公布号 JPH08107406(A) 申请公布日期 1996.04.23
申请号 JP19940242804 申请日期 1994.10.06
申请人 FUJITSU LTD 发明人 KAWAHARA EIGO
分类号 H04L29/14;H04L7/00;H04L7/02;H04L7/033;(IPC1-7):H04L7/02 主分类号 H04L29/14
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