| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a memory cycle time can be shortened appropriately while securing reliability of operation. SOLUTION: A semiconductor memory (DRAM) is constituted by providing a memory cell array section 10, an address specifying section 20, an input/output section 30 of memory data, a sense amplifier 40, a signal generating circuit 50, and the like. A row address decoder 22 constituting the address specifying section 20 is provided with a row selection latch circuit 23 holding a selected word line WL at a start state even after change of a row address XA. Also, the sense amplifier 40 is provided with a data latch circuit A 45 and a data latch circuit B 46 holding respectively and independently data of a memory cell MC amplified by the amplifier 40 and connected to two different word line WL or returning held data to the sense amplifier 40 again. |
