| 摘要 |
<p>In a synchronous processing circuit in the figure, an LPF (1) separates a vertical synchronizing separation signal (6) from a composite signal (5) from the outside, a 1/2 frequency division circuit (4) outputs a vertical phase detection signal (9) obtained by dividing the vertical synchronizing separation signal (6) into 1/2, a phase delay unit (2) to which the composite signal (5) is input outputs a plurality of different phase-delayed horizontal synchronizing signals (19 to 24), and a vertical synchronizing signal reproducing circuit (3) uses the vertical synchronizing separation signal (6) and the plurality of phase-delayed horizontal synchronizing signals (19 to 24) to output a vertical synchronizing signal (8) for which a phase relation with a horizontal synchronizing signal is determined.</p> |
