发明名称 Method, system, and computer program product for interconnecting circuit components with track patterns for electronic circuit designs
摘要 Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.
申请公布号 US9396301(B1) 申请公布日期 2016.07.19
申请号 US201414292166 申请日期 2014.05.30
申请人 Cadence Design Systems, Inc. 发明人 Lee Yinnie;Markham Jeffrey;Ruehl Roland;Sharma Karun
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Vista IP Law Group, LLP 代理人 Vista IP Law Group, LLP
主权项 1. A computer implemented method for interconnecting circuit components with track patterns for electronic designs, comprising: identifying an electronic design including a source pin and a destination pin; identifying or determining a transition pattern for interconnecting the source pin and destination pin at least by selecting multiple routing tracks from one or more track patterns, wherein the one or more track patterns respectively correspond to one or more legal combinations of widths that are arranged in one or more predetermined permissible sequences and are associated with the multiple routing tracks, and a routing track in the multiple routing tracks has zero-width; and interconnecting, at one or more track pattern modules stored at least partially in memory and including or functioning in conjunction with at least one processor in a computing system, the source pin and the destination pin based at least in part upon the transition pattern.
地址 San Jose CA US