Memory apparatus

摘要

The present disclosure provides a memory apparatus including a memory cell array, a plurality of sense amplifiers, at least one first comparing circuit, and a plurality of second comparing circuit. The memory cell array includes a plurality of memory cells. Each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal. The first comparing circuits compares the data signals of first and second sense amplifiers with a first tag to generate a first comparing result. The second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.

主权项

1. A memory apparatus, comprising:
a memory cell array, comprising a plurality of memory cells; a plurality of sense amplifiers, coupled to the memory cell array, and each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal; at least one first comparing circuit, coupled to a first sense amplifier and a second sense amplifier, wherein the first comparing circuits compares the data signals of the first and second sense amplifiers with a first tag to generate a first comparing result; and a plurality of second comparing circuits, respectively coupled to the sense amplifiers which are not coupled to the first comparing circuit, wherein the second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.