| 发明名称 | Circuit having a non-symmetrical layout | ||
| 摘要 | A circuit comprises a first voltage line, a second voltage line parallel to the first voltage line, and a bit line between the first voltage line and the second voltage line. The bit line is separated from the first voltage line by a minimum distance allowed by a design rule. The bit line is closer to the first voltage line than to the second voltage line. A first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line. | ||
| 申请公布号 | US9431066(B1) | 申请公布日期 | 2016.08.30 |
| 申请号 | US201514658982 | 申请日期 | 2015.03.16 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Chen Jui-Lin;Chang Feng-Ming;Huang Huai-Ying;Lim Kian-Long;Wang Ping-Wei |
| 分类号 | G11C5/06;G06F17/50;G11C7/18;G11C5/04;G11C5/02;G11C11/4097 | 主分类号 | G11C5/06 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A circuit, comprising: a first voltage line; a second voltage line parallel to the first voltage line; and a bit line between the first voltage line and the second voltage line, the bit line being separated from the first voltage line by a minimum distance allowed by a design rule, wherein the bit line is closer to the first voltage line than to the second voltage line, and a first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line. | ||
| 地址 | TW | ||