| 摘要 |
PURPOSE:To reduce a holding current of a memory cell and to increase a read current by providing an impedance means whose impedance is changeable to a loading means of the memory cell employing a bipolar transistor. CONSTITUTION:Transistors Q2 and Q3 used for impedance means whose impedance are changeable are connected in parallel to a load means of a memory cell employing read transistors Q0 and Q1 and bipolar transistors of information holding transistors Q0' and Q1'. When the Q0, etc., are in an off state, a read current from the Q0 to a data line LD0 becomes large due to a large resistance RC0. When a potential difference between both ends of the resistance RC0 exceeds a voltage in the regular direction of a clamp diode D0, a diode D1 operates. Then the transistor Q3 is turned on, and a current flowing in the Q3 is supplied to the base of the Q0 in parallel, whereby the potential difference between both ends of the resistance RC0 becomes small. Accordingly, a holding current of the memory cell can be reduced, while a read curent can be increased, and a memory circuit with a large bit capacity can be formed. |
