| 摘要 |
A clock signal produced by a master oscillator is monitored continuously by a detector circuit having a local oscillator which is stabilized in frequency by injection of the master clock signal. The master clock signal is first divided and the divided clock signal is then retimed by the stabilized lock clock signal. The retimed, divided clock signal is then shifted by one complete clock cycle. If the master oscillator clock signal is valid, the retimed clock signal and its shifted counterpart will always assume opposite logic values. The detector circuit generates a logic output signal which assumes a logic 0 value when the two signals are in opposite states, indicating a valid clock condiiton, and a logic 1 value when the signals have the same logic state, indicating an invalid clock condition.
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