| 摘要 |
The circuit comprises a clock unit which receives clocks for reading input signals periodically, the first D flip-flop which is to receive input signals, the second D flip-flop which is to input the clocks from the clock unit, the first logic product and the first sum processing unit which are to input the outputs of the first D flip-flop and the second D flip-flop respectively, the second logic product processing unit which is to input the output of the second D flip-flop and the semi-output of the first D flip-flop, the third logic product processing unit which inputs the output of the first logic product processing unit and input signals, the second logic product processing unit which is to provide the outputs of the first and the third logic product processing units to the input terminal of the second D flip-flop, and the third logic sum processing unit which eliminates noise from the outputs of the second and the third logic product processing units.
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