发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To obtain a semiconductor memory circuit in which a sense current is increased when a selection memory cell is set to continuity and in which the gain of a sense amplifier can be reduced by a method wherein the semiconductor memory circuit is provided with a circuit which comprises a digit line and a current route at a ground potential. SOLUTION: When a selection memory cell is set to continuity, a current flows to a ground potential via the selection memory cell and a resistance R01 at a current intensification circuit 21, a potential at a node A is raised, a transistor N01 is set to continuity, and a current to the ground potential from a digit line DG flows. That is to say, a current intensification route is added, via the transistor N01, to a normal current route to the ground potential via the selection memory cell from a sense amplifier 1 in conventional cases. The intensification circuit can reduce a continuity resistance as compared with an ordinary current route via a memory cell because it is not via a block selector and a cascade memory cell, and a sense current to the ground potential from the sense amplifier 1 can be increased. Consequently, a semiconductor memory circuit is hardly subjected to the influence of a noise due to the operation or the like of other circuits.</p>
申请公布号 JPH09180474(A) 申请公布日期 1997.07.11
申请号 JP19950333068 申请日期 1995.12.21
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 HIRANO MASANORI
分类号 G11C17/00;G11C16/06;(IPC1-7):G11C16/06 主分类号 G11C17/00
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