发明名称 STATIC SEMICONDUCTOR MEMORY AND ITS TEST METHOD
摘要 PROBLEM TO BE SOLVED: To reduce a cost for testing. SOLUTION: When a potential of a node N1 is made a 'H' level at the time of performing a test. Therefore, voltage to which power source voltage from a power source 41 is dropped by a drop circuit 81 is given to a power source voltage supplying line PL2 at the time of performing a test. On the other hand, a potential of a node N1 is made a 'L' level at the time of normally using. In this case, power source voltage from the power source 41 is given to the power source voltage supplying line PL2. The power source voltage supplying line PL2 is connected to a load element of a memory cell, at the time of performing a test, voltage given to the load element of the memory cell is smaller than that at the time of normally using. Therefore, a potential difference between two storage nodes of the memory cell can be made smaller than that at the time of normally using. Therefore, the same state as a state in which a SRAM is placed under low temperature environment can be realized.
申请公布号 JPH10144096(A) 申请公布日期 1998.05.29
申请号 JP19960303095 申请日期 1996.11.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 KAWAMURA HIDEYOSHI
分类号 G01R31/28;G11C11/413;G11C29/06;G11C29/46;H01L21/8244;H01L27/11;(IPC1-7):G11C29/00;H01L21/824 主分类号 G01R31/28
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