发明名称 METHOD FOR REDUCING PROGRAM CLOCK REFERENCE JITTER OF MPEG OVER ATM, REDUCING DEVICE AND MPEG DECODING DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a system time clock which reduces jitter by controlling a PCR with a received program clock reference PCR, a system time clock STC at the time of receiving, the cycle in an encoding device output of a transport stream packet, a packet transfer time in a device input and tolerance as specific relations. SOLUTION: In an encoding device output of a transport stream packet of an MPEG signal, a cycle is T, a packet transfer time in a device input is δand a tolerance is Δ. PCR jitter is reduced by correcting a PCR to PCR-(T-δ) when |PCR-STC|>T-δ-Δ is true and also sign (PCR-STC)>0 is true, correcting the PCR to PCR+(T-δ) when |PCR-STC|>T-δ-Δ is true and also sign (PCR-STC)>0 is false and not correcting the PCR when |PCR-STC|>T-δ-Δ is false.
申请公布号 JPH11234308(A) 申请公布日期 1999.08.27
申请号 JP19980329922 申请日期 1998.11.19
申请人 NEC CORP 发明人 OSAKI FUMIMASA
分类号 H04N19/102;H04L7/00;H04L12/28;H04L12/70;H04L12/951;H04N7/24;H04N19/00;H04N19/134;H04N19/196;H04N19/423;H04N19/44 主分类号 H04N19/102
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