METHOD FOR DESIGNING PLL(PHASE LOCKED LOOP) FREQUENCY SYNTHESIZER HAVING HIGH-PURITY FREQUENCY SPECTRUM AND SWITCHING SPEED

摘要

PURPOSE: A method for designing PLL(Phase Locked Loop) frequency synthesizer having a high-purity frequency spectrum and switching speed is provided, which is useful for a communication system of a commercial bluetooth system and a transform of a very high speed data information and high speed frequency hopping by simultaneously satisfying a high purity frequency spectrum and a very high speed switching speed. CONSTITUTION: A frequency synthesizer of a hybrid structure mixes an open-loop composing method for driving a voltage control oscillator(VCO)(10) by a D/A(digital/analog) convertor output and a closed-loop composing method of a reference PLL(phase locked loop). A high-purity and very high speed frequency synthesizer is designed as using a relationship of a system variable(a loop filter band width and a phase margin) and a capacity parameter(a switching time, a phase noise, and maximum overshoot).