Method to reduce K value of dielectric layer for advanced FinFET formation

摘要

Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.

主权项

1. A method of forming a gate, comprising:
transferring a substrate having a 3D structure comprising a gate dielectric structure disposed adjacent to a dummy gate structure into a plasma processing apparatus; removing the dummy gate structure; and exposing a vertically oriented portion of the gate dielectric structure to ions with the plasma processing apparatus, wherein one or more ion bombardment angles are selected in response to an aspect ratio of the 3D structure, and wherein the ions create at least one void within the gate dielectric structure.