| 摘要 |
PURPOSE:To attain the high speed operation of a counter circuit by using a control circuit so as to control a load (preset) pulse to a counter and the generating timing of a latch pulse to a register. CONSTITUTION:The state of a control circuit B' is transited from the standby end S1 to a latch S2 by a pulse signal INTR inputted to the control circuit B' and a register D is set to the latch state by a latch pulse *LAT. In this case, when an input pulse SPup or SPdn exists, the control circuit B' keeps the present state by an enable pulse ENB to keep the latch state. When neither the input pulse SPup nor SPdn is inputted, the control circuit B' is transited from the latch state S2 to the load S3 by an enable pulse ENB of negative logic from an OR circuit F. In this case, a load pulse *LD is outputted, a counter C' is preset and the state of the control circuit B' is transited from the load S3 to the standby end S1 again.
|
