| 摘要 |
<p>PURPOSE:To obtain the circuit of high operation reliability by constituting the circuit in such a way that an output part reads the invalid data part of input data twice. CONSTITUTION:When an input-side clock is delayed with respect to an output- side clock, a phase supervisory part 41 outputs a detection signal ALM2. When the invalid data part of input data continues for several bits, a detection signal DS is outputted from a bit continuation detection part 42. An enable signal EN2 is outputted from the detection signal ALM2 and the detection signal DS and it is supplied to an output part 40 from a two-time read instruction part 43. The invalid part of input data is read twice in the output part 40 and a bit phase is synchronized by the two-time reading.</p> |
