发明名称 HIGH-PERFORMANCE DIGITAL IC PACKAGE USING BGA-TYPE I/O FORMAT AND SINGLE-LAYER CERAMIC PLATE BOARD BY BIMETAL FILLING VIA
摘要 PROBLEM TO BE SOLVED: To enable strict control of coplanarity and enable a number of connections in a small unit area without increasing the number of layers, by using a pole grid array format and a single-layer ceramic plate board having a number of vias which are filled with bimetal and precisely positioned. SOLUTION: On a single-layer board having predetermined patterns of vias 22, 25, a plurality of circuit tracers extending from a plurality of wire bonding pads 19 or flip-flop mounting pads are provided for the plurality of vias 22, 25 in order to cause electric contact with each other. A protector 32 protects the vias 22, 25, the tracers, the wiring bonding pads 19, wire bonds 20 and a die 30 from the environment. On a surface opposite to the board surface where the die 30 is provided, a plurality of conductive balls 17 are provided. Thus, strict control of coplanarity is enabled without increasing the number of layers.
申请公布号 JPH09213829(A) 申请公布日期 1997.08.15
申请号 JP19960143210 申请日期 1996.06.05
申请人 CIRCUIT COMPONENTS INC 发明人 NOOMAN ERU GURIINMAN;EMU PII RAMACHIYANDORA PANITSUKAA;JIYOOJI EMU HERUNANDEZU
分类号 H01L23/12;H01L23/055;H01L23/31;H01L23/367;H01L23/498 主分类号 H01L23/12
代理机构 代理人
主权项
地址