Control circuit of an output buffer, particularly for a non-volatile memory device

摘要

The invention relates to a control circuit (1) for an output buffer, of the type which comprises a first input terminal (I1) receiving a first enable signal (OEn) and a second input terminal (I2) receiving a second enable signal (CEn), as well as first (O1) and second (O2) output terminals to generate first (OE_L) and second (OE_H) partial enable signals to transfer discrete sets of data bits, the first (I1) and second (I2) input terminals being coupled to the first (O1) and second (O2) output terminals through a multiplexer (2), the control circuit (1) comprising a synchronization circuit (7) for linking the partial enable signals (OE_L,OE_H) operatively to a synchronization signal (SYNC) of the pulse type being synchronous with the loading of the output buffer, the synchronization circuit (7) being connected between an output terminal (O3) of said multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1). <IMAGE>