| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a capacitive load of a bit line by increasing capacity of a non-volatile semiconductor memory, and to increase operation speed by setting voltage satisfying each condition of erasing a memory cell, programming, and reading out. SOLUTION: A memory cell array is divided into plural blocks 13, 14, and bit lines specified by the same column address of each block are constituted with divided bit lines BLa, BLb. The bit lines BLa, BLb of each block are selectively connected to a main bit line BL connected to a column address decoder by selection transistors 15, 17, further, connected selectively to a potential line ARGND by selection transistors MOS 16, 18. Thereby, a capacitive load of a bit line is reduced, also, a bit line being not selected is connected to the potential line ARGND and made to a discharge state.</p> |
