| 摘要 |
PROBLEM TO BE SOLVED: To resolve problems in which delay time is under estimated in a delay calculation with the real delay time becoming larger than the delay time stored in a library by the parasitic capacitance between them and patterns in a cell when the wiring exists on the cell. SOLUTION: In the apparatus for extracting a semiconductor circuit, the uppermost layer wiring used in the patterns in the cell is detected, virtual wiring patterns are wired on the all wiring tracks on the cells that have the wiring layer by one layer higher than this uppermost layer wiring, parasitic capacitance is extracted about all patterns including them, by calculating delay time of layout wiring data in consideration of this parasitic capacitance, delay information library data is made more accurate, and thus the apparatus for automatic layout wiring and the library distribution system are able to take advantage of this. |
