发明名称
摘要 <p>PURPOSE:To shorten write and read time by setting the next data to other parts while outputting partial data to be set in a try state buffer or a latch circuit having a capacity of a plurality of sense amplifiers. CONSTITUTION:A buffer 9 or a latch circuit 7 whose capacity is designed for a plurality of sense amplifiers is connected between a column switch 6 which selects a data line connected with both input and output and the try state buffer 9 connected with a write section of a memory array 1 or the switch 6 and a sense amplifier 10 connected with the read section of the memory array 1. While data set into the circuit 7 is being partially output, the subsequent data is set into a different part of the circuit 7. This construction makes it possible to increase an apparent write speed and read speed to and from the memory array 1 and hence shorten both write time and read time.</p>
申请公布号 JP3218471(B2) 申请公布日期 2001.10.15
申请号 JP19900292145 申请日期 1990.10.31
申请人 发明人
分类号 G11C16/02;G11C16/06;(IPC1-7):G11C16/02 主分类号 G11C16/02
代理机构 代理人
主权项
地址