发明名称 TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER
摘要 The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
申请公布号 US2008315196(A1) 申请公布日期 2008.12.25
申请号 US20080196032 申请日期 2008.08.21
申请人 AGHABABAZADEH MAJID;ESTABIL JOSE J;PAKDAMAN NADER;STEINBRUECK GARY L;VICKERS JAMES S 发明人 AGHABABAZADEH MAJID;ESTABIL JOSE J.;PAKDAMAN NADER;STEINBRUECK GARY L.;VICKERS JAMES S.
分类号 H01L23/544;G01R31/28;G01R31/317;G01R31/3185;H01L21/66 主分类号 H01L23/544
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