Data transfer clock recovery for legacy systems

摘要

The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate.

主权项

1. A deserializer circuit comprising:
a sampler circuit configured to receive a stream of bits transmitted at a transmission rate and sample the received stream of bits at a reception rate higher than the transmission rate; a symbol assembly circuit coupled with the sampler circuit, and configured to group a portion of the sampled stream of bits into a frame; and a bit alignment circuit coupled with the symbol assembly circuit, and the bit alignment circuit configured to detect a frame slip when two sampled bits within the frame have different values, and upon detecting the frame slip, the bit alignment circuit configured to realign the frame until the two sampled bits share a same bit value representing a data bit output of the received stream of bits.