| 摘要 |
An image processor inputs coded image data, which is comprised of a plurality of resolution levels, and image processor thereafter rearranges and stores the coded image data into image memory 4 so that the resolution levels of the coded image data can be stored into a consecutive address area of the image memory 4. Thereafter DMA controller 11 reads out the coded image data stored in the image memory 4 into decoder 7 by accessing the consecutive address area of the image memory 4. The decoder 7 decodes the coded image data transferred at high speed.
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