| 摘要 |
PROBLEM TO BE SOLVED: To generate and output an M sequence or a gold code sequence with the difference of a desired shift amount simultaneously. SOLUTION: A prescribed M sequence is outputted by adding outputs prescribed taps of a shift register 11 by a modulo 2 adder 13 and feeding back the sum. On the other hand, outputs of desired stage of the shift register 11 are subject to modulo 2 addition at a combination logic circuit 14, a shift series circulatingly shifted by a desired bit with respect to the M sequence is outputted simultaneously. The tap position received by the combination logic circuit 14 is set by a control signal and an optional shift sequence is outputted. Furthermore, a counter 15 restores the shift register 11 to an initial state for each prescribed timing to outputs only part of one period repetitively. A gold code sequence and its shift sequence are simultaneously outputted by using the two code generating circuits. Furthermore, an optional bit pattern is inserted to the generated code sequence. |
