| 摘要 |
A lock determination circuit raises the electric potential of the input of a lock determination gate after the lock state is determined, thereby reducing (the period of) the current flowing through the lock determination gate. In the circuit, the input level of the lock determination gate is forcibly pulled up immediately after the lock state is determined, so as to reduce the current flowing through the lock determination gate. A pull-up transistor and a delay circuit may be used, wherein the delay circuit is activated when the lock state is determined, and the pull-up operation is performed by setting the pull-up transistor to the ON state for a predetermined period by using the delay circuit.
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