| 发明名称 |
3D field programmable gate array system with reset manufacture and method of manufacture thereof |
| 摘要 |
A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die. |
| 申请公布号 |
US9374094(B1) |
申请公布日期 |
2016.06.21 |
| 申请号 |
US201414470901 |
申请日期 |
2014.08.27 |
| 申请人 |
Altera Corporation |
发明人 |
Xiao Ping |
| 分类号 |
H03K19/017;H03K19/08;H03K19/0175;H01L25/16;H03K19/177;H03K17/22 |
主分类号 |
H03K19/017 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of manufacture of a 3D field programmable gate array (FPGA) system comprising:
mounting a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; coupling a heterogeneous integrated circuit die to the FPGA die; and configuring a 3D power on reset (POR) output by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die. |
| 地址 |
San Jose CA US |
