发明名称 Data line arrangement and pillar arrangement in apparatuses
摘要 Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).
申请公布号 US9431421(B2) 申请公布日期 2016.08.30
申请号 US201514850781 申请日期 2015.09.10
申请人 Micron Technology, Inc. 发明人 Vu Luyen;Helm Mark A.
分类号 H01L27/115;H01L29/16;H01L29/04 主分类号 H01L27/115
代理机构 Wells St. John P.S. 代理人 Wells St. John P.S.
主权项 1. An apparatus, comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement; the hexagonally closest packed arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars, wherein each of the different pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of a plurality of data lines; and wherein each of the pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD); the pillars and SGD being supported by a base comprising monocrystalline silicon.
地址 Boise ID US