发明名称 POWER FAILURE PROCESSING SYSTEM IN COMPUTER SYSTEM
摘要 <p>PURPOSE:To attain inexpensive battery device storing the content of a main storage device for a long time at power failure by allowing a control program to read and write the present state of a interruption device of a CPU. CONSTITUTION:When a fault takes place in an input power supply PS27 while a computer is in operation, a backup battery 28 is driven, a power is fed to a main storage device MMU22 and unexpected power supply interruption is applied to the CPU21 for a prescribed time. Thus, the supervisory program activated on the CPU21 uses an interruption control device 31 to read the content of an FF representing each interruption activating state at present and it is stored in an address of the MMU22 is response to each interruption level. Then when a prescribed time is elapsed, the supply of input power to the CPU21 and a system controller SCP26 is stopped and the content of the MMU22 is kept for a long time by the battery 28. Thus, the battery device storing only the content of the MMU22 for a long time at a power failure is formed inexpensively.</p>
申请公布号 JPS6121520(A) 申请公布日期 1986.01.30
申请号 JP19840140629 申请日期 1984.07.09
申请人 MITSUBISHI DENKI KK 发明人 YOSHIDA MIKIO;TSUTAKI FUMIO
分类号 G06F1/30;G06F1/00 主分类号 G06F1/30
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