| 摘要 |
<p>The differentiator circuit comprises a first current memory cell comprising capacitor C2, switch S2, transistor T2 and transistor T3 and a second current memory cell comprising capacitor C1, switch S1 and transistor T1. During one portion phi 2 of each sampling period the input current i minus the current produced by transistor T1, which acts as a current source when switch S1 is open, together with appropriate bias currents to allow bi-directional input currents to be handled is fed via switch S3 to the first current memory cell. During another portion phi 1 of each sampling period the input current plus an appropriate bias current is fed to the input of the second current memory cell. The switches S3 and S2 are open so transistor T2 acts as a current source giving an output via switch 54 at output 17 in addition to the output 15. The differentiated output signal is available throughout at output 15 but only during the portion phi 2 of each sampling period at output 17. The circuit corresponds to a backward Euler mapping from continuous time ideal differentiators. Corresponding circuits giving forward Euler and bilinear mappings are also disclosed as are circuits for lossy differentiators. Various alternative current memory cells are also disclosed.</p> |
