| 摘要 |
PURPOSE:To reduce the number of faces of a frame memory by providing a memory read generator, a write address generator, an address comparator circuit, and an address generator control circuit. CONSTITUTION:An input signal 3 is written in a memory 61. The write position is determined by a write address 36 outputted by a write address generating circuit 32. All signals 3 are normally written in such a manner; but when the address 36 precedes a read address 35 and is close to this address 35, write of the pertinent picture and its subsequent pictures is stopped, and the address 36 is returned to the head of the picture. Meanwhile, read is performed at any time by an encoding picture signal 5, and the reading start is delayed to prevent the address 35 from overtaking the address 36 when the address 35 is close to the address 36. After the address 36 is advanced, the read address does not catch up with the address 35 because the advance speed of the address 36 is higher than that of the address 35. Thus, the conventional processing capability is maintained and the number of faces of the frame memory is reduced to miniaturize a device. |
