Rapid access memory circuit - uses groups of cells in memory with transfer through register that has bits beyond word length to aid mask access

摘要

The memory circuit has memory cells (2) arranged in a matrix (1) that is addressable in groups (31-34) of cells by decoding an address (AD1). The data is carried on a bus (20) having as many bits as there are cells in each memory group (31-34). A register (43,44) connected to the bus exchanges data with the cell groups. The size of the register exceeds the word size and during a memory access cycle transfers a number of bits exceeding the word size. The extra bits enable masking to provide faster access to a memory zone or memory port. ADVANTAGE - Increased memory bandwidth for faster transfer of data, particularly with multi-port memory.