| 摘要 |
PURPOSE: A noise eliminating circuit is provided to eliminate a noise of a clock signal regardless of its magnitude by varying a width of a pulse signal generated when detecting rising and falling edges of the clock signal using a delay circuit. CONSTITUTION: The first edge detecting part(20) receives a clock signal(CLK) to detect a rising edge of the clock signal. When the rising edge is detected, the first edge detecting part(20) determines a pulse width of a delay signal(N3) of the first delay part(10) and outputs a pulse signal(N1) based on determination of the pulse width. The first delay part(10) comprises a latch and a gate array and generates the delay signal(N3) for determining a width of the pulse signal(N1) outputted from the first edge detecting part(20). The second edge detecting part(30) receives an inverted clock signal(CLK) to detect a rising edge of the received clock signal. When the rising edge is detected, the second edge detecting part(30) determines a pulse width of a delay signal(N4) of the second delay part(40) and outputs a pulse signal(N2) based on determination of the pulse width. The second delay part(40) comprises a latch and a gate array and generates the delay signal(N4) for determining a width of the pulse signal(N2) outputted from the second edge detecting part(30). An RS latch(50) receives the pulse signals(N1, N2) to restore the clock signal(CLK).
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