| 摘要 |
A bus arbitration circuit for arbitrating data transfers from a plurality of master devices to a slave device connected to the plurality of master devices through a bus includes an ID generation unit for arbitrating the data transfers received from the plurality of master devices and outputting identification information of a master device that output the requests in an order of an issuance of the requests or priority, and a request processor for processing the requests according to the master device identification information received from the ID generation unit. At least the request processor is provided to each of the slave device.
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