Logical unit address assignment

摘要

Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.

主权项

1. A logical unit of a memory device, said logical unit comprising:
a memory array; stored memory device configuration data, wherein the memory device configuration data is indicative of a memory device type containing the logical unit; an address input configured to receive an address input control signal; an address output configured to output an address output control signal; a counter having a count value; and control circuitry configured to assign a logical unit address to the logical unit in response to said address input control signal and said address output control signal, said logical unit address being based on said count value, and further configured to determine the memory device type based upon the stored memory device configuration data and to determine how many logical units should be assigned logical unit addresses based on the determined memory device type.