发明名称 Determining soft error infliction probability
摘要 A method, system and product for determining error infliction probability or probability. The method comprises obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles; and outputting the SEIP of the node.
申请公布号 US9430599(B2) 申请公布日期 2016.08.30
申请号 US201514601312 申请日期 2015.01.21
申请人 OPTIMA DESIGN AUTOMATION LTD 发明人 Mazzawi Jamil Raja;Mouallem Ayman Kamil
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Tutunjian & Bitteto, P.C. 代理人 Tutunjian & Bitteto, P.C.
主权项 1. A computer-implemented method comprising: obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein the consecutive cycles are successive cycles after the cycle, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles, wherein the critical node is a conditional critical node having a condition on values of the circuit, wherein the condition is enabled in an enabling cycle, wherein the condition is held at the enabling cycle; wherein a discrepancy between a simulated value and a recorded value of a conditional critical node at the enabling cycle indicates a soft error; and outputting the SEIP of the node.
地址 Nazareth IL