| 摘要 |
PURPOSE:To vary a data transfer speed and to use the ability of a DMA bus effectively, by using a basic clock which varies in period according to whether the intervals of transfer request from a preferential channel exists within a specific time or not. CONSTITUTION:The detecting circuit 11 of an input/output channel device 1 receives a DMA data transfer request REQ-A from another preferential channel and informs a basic clock generating circuit 12 of whether the interval is within the specific time or not. The circuit 12 applies a clock CP1 which has a different period (e.g. double period) on the basis of the detection result to a channel control signal generating circuit 13. The signal generating circuit 13 sends signals SA3, SBa, and SA2 to registers 16 and 17, and a buffer 14 on the basis of the clock CP1 to control the input and output of data transfer between a DMA bus 5 and an external interface 18. The data transfer speed in this case varies with the speed of the controlled clock CP1. |
