Method and apparatus for program verification of a field programmable logic device

摘要

A program verification circuit and technique adapted for use with a programmable logic array having at least one logic gate and first and second inputs thereto. A unique and novel operation is afforded by the present invention in that a method is provided of verifying the program of a field programmable logic array having a logic gate and at least first and second inputs thereto. The method of the invention includes the steps of: a) shifting verification control data through a shift register; b) selecting the first input of the logic gate by applying a first control signal to the first input of the logic gate in response to the output of the shift register; and c) deselecting the second input of the logic gate in response to the output of the shift register. A particularly novel aspect of the invention is provided in that the step of shifting verification control data through the shift register includes the steps of providing a first control signal (e.g. a logical "0") for selecting an input (or column) of the logic gate and supplying a second control signal (e.g. a logical '1') for deselecting all other inputs of the logic gate. The step of supplying a second control signal for deselecting all other inputs of the logic gate includes the step of supplying plural second control signals, one for n-1 deselected inputs of an n input logic gate.