Semiconductor memory device

摘要

An address generating circuit and an address switching circuit of a DRAM output address signals A0 to A11 according to a refresh cycle time set by the user being less than a predetermined value, and output address signals A0 to A10 according to the refresh cycle time being the predetermined value or more. A row decoder selects one word line in response to the signals A0 to A11, and selects two word lines in response to the signals A0 to A10. Since refresh is carried out by selecting two word lines when the refresh cycle time is at the predetermined value or more, disappearance of data can be prevented.