| 摘要 |
A fast memory system including one or more asymmetrical sense amplifiers precharged to a first logic state and optimized to slew very fast towards the first logic state. Each sense amplifier is coupled to a corresponding pair of complementary bit lines, which are preferably precharged. When enabled, each sense amplifier tends towards an opposite, default logic state opposite the first logic state when sensing the precharged bit lines. Control logic enables a corresponding precharge amplifier to precharge the bit lines, and then enables the sense amplifier after the assertion of a clock signal. Also, the control logic enables a corresponding pull-up device to precharge the output of each sense amplifier. Thus, the sense amplifier begins in the first, precharged logic state and slews towards the opposite, default logic state. The control logic then asserts a word line select signal to a corresponding memory cell, which drives a voltage differential on the bit lines to assert a data bit. If the data bit supports the default state, then the sense amplifier switches to the default state. However, if the data bit supports the first state, the sense amplifier quickly responds and slews back to the first state. In this manner, either logic state is achieved very quickly. Preferably, an invertor is coupled to the sense amplifier having an input switch-point set to favor the default logic state.
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