| 摘要 |
PURPOSE: A test circuit is provided to test a memory in a merged memory with logic(MML) chip efficiently by realizing a built in self test(BIST) logic and a direct memory test(DMT) structure in the MML chip. CONSTITUTION: A test pad(1) receives a test signal, and an input and output pad(2) inputs and outputs test data. An input pad(3) receives a test control signal, and a clock pad(4) receives a clock signal necessary for a test operation. A logic block(7) stores test logics, and a DRAM controller(6) controls an access of a DRAM core block(5) in response to the test logics of the logic block(7). The first select output part(8a) outputs the clock signal of the clock pad(4) to the logic block in response to the test signal. The second select output part(8b) outputs the test control signal from the input pad(3) to the logic block(7) in response to the test signal. The third select output part(8c) outputs the test data to the logic block in response to the test signal. The fourth select output part(8d) outputs signals(doe_d, doe_1) to a buffer of an input/output pad block in response to the test control signal. The sixth select output part(8f) outputs the test data of the third select output part and a write control signal of the DRAM controller in response to the test control signal. A buffer(9a) outputs the test control signal of the second select output part(8b) to a wd terminal of the DRAM core block(5). The eighth select output part(8h) outputs the test control signal and the address signal of the DRAM controller to an input terminal(in) of the core block(5) in response to the test control signal. The seventh select output part(8g) outputs a read signal of the core block in response to the test control signal. A buffer(9b) outputs an output signal of the seventh select output part(8g) to the controller(6). The fifth select output part(8e) outputs an output signal of the logic block and an output signal of the seventh select output part(8g) to the pad(2) in response to the test control signal.
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