| 摘要 |
In a memory circuit, an address signal generating means (70) comprising a first counter (72) which outputs first ouput data (Q1) for designating the address signals of object cells from a plurality of memory cells in a memory unit (10) successively, a second counter (74) which outputs second output data (Q2) for specifying the address signals of the memory cells of the memory unit (10) successively every time the address signal of one object cell is designated, an output control circuit (76) which outputs the second output data (Q2) as the third output data (Q3) selectively in accordance with control signals INH and an arithmetic circuit (78) which generates address signals (Q4) by arithmetically processing the first output data (Q1) and the third output data (Q3). With this constitution, it is unnecessary to prepare a memory in which address signals based upon a test pattern are stored, input the address signals from the memory successively, and use a tester exclusively for a memory test.
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