| 摘要 |
<p>A delay locked loop (DLL) circuit in which phase adjustment is performed in consideration of external load. Specifically, the DDL circuit generates a control clock signal with a predetermined phase relation by delaying a reference clock signal. The delay time of an output buffer, which varies depending on external load, is measured in order to adjust the delay of a second variable-delay circuit in a feedback loop in accordance with the measured delay time. As a result, the timing of the output clock signal of a first variable-delay circuit, delay of which is controlled by a phase comparison circuit and a delay control circuit, is adjusted on the basis of the magnitude of the external load.</p> |
