| 摘要 |
PURPOSE: A high-frequency phase locked loop circuit is provided to improve the maximum frequency by using a CMOS(Complementary Metal Oxide Semiconductor) technology. CONSTITUTION: A computer system comprises a PLL(Phase Locked Loop) circuit(11), a crystal(18), and a logic device(22). The PLL circuit(11) provides a CLOCK_OUT signal to the logic device(22). The crystal(18) provides a CLOCK_IN signal to the PLL circuit(11). The PLL circuit(11) includes a PLL sub-circuit(12), a PLL sub-circuit(14), and an exclusive OR gate(16). The PLL sub-circuit(12) includes a 2N-dividing(divide-by-2N) circuit(20), a phase detector(24), a charge pump(26), a loop filter(28), a voltage controlled oscillator(VOC)(30), and an 11N-dividing circuit(32). The PLL sub-circuit(14) includes a 2N-dividing circuit(40), a phase detector(44), a charge pump(46), a loop filter(48), a delay circuit(50), and an 11N-dividing circuit(52).
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