发明名称 |
Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs |
摘要 |
Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.
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申请公布号 |
US7404126(B2) |
申请公布日期 |
2008.07.22 |
申请号 |
US20060308481 |
申请日期 |
2006.03.29 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
JAIN SANDEEP;ABRAHAM JAIS |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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