Clock multiplexer for generating glitch-free clock signal

摘要

A fully digital glitch-free clock multiplexer includes a monitoring circuit that automatically switches to a newly selected clock, after a defined time period, from a currently selected clock, when the currently selected clock is absent. A maximum time limit is calculated based on a min and max clock frequency ratio. The monitoring circuit operates only when the clock is being switched. This provides flexibility to software to switch the clock any time whether or not the current clock is present, and prevents the system from hanging in the absence of the clock.

主权项

1. A clock multiplexer for providing a glitch-free clock output signal, comprising:
a decoder that receives a select signal and generates first and second select signals; a first switchover control circuit that (i) receives a timer reset signal, a first clock signal, and a first enable signal, (ii) is connected to the decoder for receiving the first select signal, and (iii) generates a second enable signal, a first start timer signal, and a first stop timer signal; a second switchover control circuit that (i) receives the timer reset signal and a second clock signal, (ii) is connected to the decoder for receiving the second select signal and to the first switchover control circuit for receiving the second enable signal, and (iii) generates the first enable signal, a second start timer signal, and a second stop timer signal; a first multiplexer having input terminals for receiving the first and second start timer signals, and a select terminal for receiving the select signal, and an output terminal for outputting a start timer output signal; a second multiplexer having input terminals for receiving the first and second stop timer signals, and a select terminal for receiving the select signal, and an output terminal for outputting a stop timer output signal; a timeout control circuit that (i) receives one of the first and second clock signals, (ii) receives the start timer output signal and the stop timer output signal, (iii) performs a counting operation to generate a count value based on the start timer output signal, (iv) compares the count value with a predetermined timer value, (v) generates the timer reset signal for resetting at least one of the first and second switchover control circuits when the count value is equal to the predetermined timer value, and (vi) stops the counting operation based on at least one of the stop timer output signal and the timer reset signal; and a first combinational logic circuit that (i) receives the first and second clock signals, (ii) is connected to the first and second switchover control circuits for receiving the second and first enable signals, and (iii) outputs one of the first and second clock signals as the clock output signal based on the first and second enable signals.