Topography-aware lithography pattern check

摘要

The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.

主权项

1. A method, comprising:
receiving a layout design for an integrated circuit (IC) device; performing a lithography pattern check (LPC) simulation on a first layer of the layout design, the LPC simulation including a topography-aware simulation model, the topography aware simulation model using data indicating topography variation of a second layer underlying the first layer to determine defocus values for areas of the layout design; and using the defocus values determined by the LPC simulation, identifying areas of the layout design that have defocus values that are outside a defined depth of focus tolerance range as potential hot spots of the layout design.