发明名称 |
Multi-wire open-drain link with data symbol transition based clocking |
摘要 |
A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions. |
申请公布号 |
US9374216(B2) |
申请公布日期 |
2016.06.21 |
申请号 |
US201414220056 |
申请日期 |
2014.03.19 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Sengoku Shoichiro;Cheung Joseph;Wiley George Alan |
分类号 |
H04L7/033;H03K5/1534;H03K3/017;H03K5/153;H03L7/081;H03K5/13;H03K5/134;H03K19/00;H03K5/14;H03K5/00;H04L7/00 |
主分类号 |
H04L7/033 |
代理机构 |
Loza & Loza, LLP |
代理人 |
Loza & Loza, LLP |
主权项 |
1. A method for generating a clock signal, comprising:
receiving one or more signals from a multi-wire communication interface, wherein a sequence of symbols is encoded in the one or more signals; determining a first transition in the one or more signals, wherein the first transition comprises a rising edge; generating a first clock pulse on the clock signal responsive to the first transition and after a preconfigured first interval provided by delaying the first clock pulse using a first delay circuit; determining a second transition in the one or more signals, wherein the second transition comprises a falling edge; and generating a second clock pulse on the clock signal responsive to the second transition and after a preconfigured second interval provided by delaying the second clock pulse using a second delay circuit, wherein the preconfigured first interval and the preconfigured second interval have different durations. |
地址 |
San Diego CA US |