发明名称 PWM output apparatus and motor driving apparatus
摘要 A PWM output apparatus includes a calculating circuit configured to calculate an output width of a PWM output signal of a first signal and a second signal, which have phases different from each other, based on a command value of a PWM output. A comparing circuit compares the output width and a reference period which is set longer than a predetermined dead time period. A PWM output signal generating circuit outputs the PWM output signal to a dead time inserting block as a corrected PWM output signal, when a set/clear signal generating circuit outputs the set signal, and carries out a correction of setting the first signal of the PWM output signal to be inactive to output to the dead time inserting block as the corrected PWM output signal, when the set/clear circuit outputs the clear signal. The dead time inserting block corrects the corrected PWM output signal.
申请公布号 US9374032(B2) 申请公布日期 2016.06.21
申请号 US201414463847 申请日期 2014.08.20
申请人 Renesas Electronics Corporation 发明人 Minami Masahiro
分类号 H02P6/04;H02P23/00;H02P27/08;H03K7/08 主分类号 H02P6/04
代理机构 Shapiro, Gabor and Rosenberger, PLLC 代理人 Shapiro, Gabor and Rosenberger, PLLC
主权项 1. A PWM signal generating method comprising: comparing, by a comparing circuit, a value indicative of a pulse width of a PWM signal and a value indicative of a reference dead time period; generating a resultant signal based on the comparison; generating, by a PWM output circuit, a PWM output signal including a first voltage signal and a second voltage signal based on the pulse width value, a value indicative of a dead time period, the resultant signal, and a clock value of a clock period; setting, by a dead time setting circuit, a signal indicative of the dead time period into the PWM output signal in response to a setting event of the first and second voltage signals; and generating, by the PWM output circuit, a target PWM output signal based on the setting of the signal, wherein said generating of the PWM output signal comprises: simultaneously generating the first and second voltage signals, the first voltage signal being set to an inactive level when the resultant signal indicates that the pulse width value is equal to or smaller than the reference dead time period value, and the second voltage signal being set to an inactive level for a period of time which equals the pulse width value; and simultaneously generating the first and second voltage signals, the first voltage signal being set to an active level for a period of time which equals the difference between the pulse width value and the dead time period value when the resultant signal indicates that the pulse width value is greater than the reference dead time period value, and the second voltage signal being set to an inactive level for a period of time which equals the difference between the pulse width value and the dead time period value, and wherein the setting of the signal indicative of the dead time period comprises: setting the dead time signal into the first voltage signal at a transition of the first voltage signal from an inactive to an active level in response to the setting event; and setting the dead time signal into the second voltage signal at a transition of the second voltage signal from an inactive to an active level in response to the setting event.
地址 Tokyo JP